I. Field of the Disclosure
This disclosure relates generally to complementary metal oxide semiconductor (CMOS) devices, and more specifically to implementing nanowire channel structures in CMOS devices.
II. Background
Transistors are essential components in modern electronic devices, and large numbers of transistors are employed in integrated circuits (ICs) therein. For example, components such as central processing units (CPUs) and memory systems each employ a large quantity of transistors for logic circuits and memory devices.
As electronic devices become more complex in functionality, so does the need to include a greater number of transistors in such devices. But as electronic devices are provided in increasingly smaller packages, such as in mobile devices for example, there is a need to provide a greater number of transistors in a smaller IC chip. This increase in the number of transistors is achieved in part through continued efforts to miniaturize transistors in ICs (i.e., placing increasingly more transistors into the same amount of space). In particular, node sizes in ICs are being scaled down by a reduction in minimum metal line width in the ICs (e.g., 65 nanometers (nm), 45 nm, 28 nm, 20 nm, etc.). As a result, the gate lengths of planar transistors are also scalably reduced, thereby reducing the channel length of the transistors and interconnects. Reduced channel length in planar transistors has the benefit of increasing drive strength (i.e., increased drain current) and providing smaller parasitic capacitances resulting in reduced circuit delay. However, as channel length in planar transistors is reduced such that the channel length is of the same order of magnitude as the depletion layer widths, short channel effects (SCEs) can occur that degrade performance. More specifically, SCEs in planar transistors cause increased current leakage, reduced threshold voltage, and/or threshold voltage roll-off (i.e., reduced threshold voltage at shorter gate lengths), and therefore, reduced gate control.
In this regard, alternative transistor designs to planar transistors have been developed. These alternative transistor designs provide for a gate material to wrap around at least a portion of a channel structure to provide better gate control over an active channel therein. Better gate control provides reduced current leakage and increased threshold voltage compared to a planar transistor of a similar footprint. An example is a complementary metal oxide semiconductor (CMOS) fin field-effect transistor (FET) (FinFET). A FinFET provides a channel structure formed by a thin Silicon (Si) “fin,” and a gate that wraps around top and side portions of the fin. FIG. 1A illustrates a conventional CMOS FinFET 100 (“FinFET 100”) as an example. The FinFET 100 includes a substrate 102, a source 104, and a drain 106. The FinFET 100 further includes fin structures 108 and 110 disposed above the substrate 102 between the source 104 and the drain 106 to form a channel structure 112. The fin structures 108 and 110 are made of a conductive material, such as Silicon (Si) for example. The FinFET 100 further includes spacer layers 114 and 116 disposed to isolate the source 104 and the drain 106, respectively, from a “wrap-around” gate 118 disposed over the fin structures 108 and 110 in a later fabrication stage. Accordingly, the gate 118 wraps around top portions and side portions (not shown) of the fin structures 108 and 110.
FIG. 2A illustrates a cross section of the FinFET 100 across an A-A line illustrated in FIG. 1A. As shown in FIG. 2A, the fin structures 108 and 110 are disposed at a lateral pitch 120 which allows the gate 118 to wrap around the top portions and the side portions of the fin structures 108 and 110. The gate 118 does not wrap under the fin structures 108 and 110. This configuration provides an effective channel width of the FinFET 100, i.e., the area of the channel structure 112 that can be controlled by an electrostatic field generated when a voltage is applied to the gate 118, that is proportional to a perimeter 122 of the fin structure 108 exposed to the gate 118. This perimeter 122 is based on a width 124 of the fin structure 108 and a height 126 of the fin structure 108. Having the gate 118 wrap around the top portions and the side portions of the fin structures 108 and 110 allows for a larger effective channel width in comparison to a planar transistor of a similar footprint. Having a larger effective channel width provides better gate control over the channel structure 112, which makes the FinFET 100 less susceptible to performance degradation due to SCEs in comparison to a planar transistor of a similar footprint. Accordingly, having better gate control over the channel structure 112 allows for a further scaling down of the FinFET 100 relative to a planar transistor of a similar footprint.
However, additional scaling down of the FinFET 100 is subject to fabrication and performance limitations. For example, a reduction of the channel length of the FinFET 100 can increase sub-threshold leakage, negatively affect gate control, and negatively affect frequency performance of a circuit employing the FinFET 100. In this regard, another example of an alternative transistor design is a conventional CMOS nanowire device. In a conventional CMOS nanowire device, a nanowire channel structure is formed by a plurality of nanowires, such as Silicon (Si) nanowires for example. A “wrap-around” gate wraps completely around each nanowire of the plurality of nanowires. FIG. 1B illustrates a conventional CMOS nanowire device 132 (“nanowire device 132”) as compared to the FinFET 100 in FIG. 1A. The nanowire device 132 includes a substrate 134, a source 136, and a drain 138. The nanowire device 132 further includes a nanowire channel structure 140. The nanowire channel structure 140 comprises nanowires 142(1-N) disposed above the substrate 134 and interposed between the source 136 and the drain 138. The nanowires 142(1-N) are configured in two (2) channel structure columns labeled 144 and 146. The nanowires 142(1-N) are made of a semiconductor material, such as Silicon (Si) for example. The nanowire device 132 further includes spacer layers 148 and 150 disposed to isolate the source 136 and the drain 138, respectively, from a gate 152 disposed over the nanowires 142(1-N) in a later fabrication stage. Accordingly, the gate 152 wraps entirely around each of the nanowires 142(1-N) of the nanowire channel structure 140.
FIG. 2B illustrates a cross section of the nanowire device 132 across a B-B line illustrated in FIG. 1B. As shown in FIG. 2B, the nanowire channel structure 140 comprises the nanowires 142(1-N), with N being 6 in this example. The channel structure columns 144 and 146 are disposed at a pitch 154, which allows the gate 152 to entirely wrap around each of the nanowires 142(1-N) of the nanowire channel structure 140. This configuration provides an effective channel width that is proportional to a perimeter 156 of the nanowires 142(1-3) of the channel structure column 144 exposed to the gate 152. In this example, the nanowires 142(1-3) are of a similar width 158 and of a similar height 160 (labeled only for the nanowire 142(3)). This configuration may allow for a larger effective channel width in comparison to a FinFET transistor of a similar footprint. For example, a larger effective channel width can be provided by the nanowire device 132 by increasing the number of nanowires 142(1-N). Accordingly, a large number of nanowires 142(1-N) may provide better gate control and increased drive strength in the nanowire device 132 that the FinFET 100.
However, fabrication and performance limitations may limit the number of nanowires 142(1-N) that can be disposed in the nanowire device 132, and therefore, limit the effective channel width therein. In particular, as shown in FIG. 2B, vertically adjacent nanowires, such as nanowires 142(1) and 142(2), are separated by a distance 162, while horizontally adjacent nanowires, such as nanowires 142(1) and 142(4), are separated by a distance 164. Thus, minimizing the distances 162 and 164 may allow for the formation of additional nanowires 142(1-N) in the nanowire device 132. Furthermore, minimizing the distances 162 and 164 may reduce the area between the gate 152 and the source 136, which may reduce parallel plate parasitic capacitance therein. In particular, the gate 152 and the source 136 are separated by the spacer layer 148, thus creating a parasitic parallel plate capacitance between the gate 152 and the source 136. Reducing the area between the gate 152 and the source 136 reduces the parasitic parallel plate capacitance between the gate 152 and the source 136, thus reducing a delay of the nanowire device 132. Reducing this delay increases the frequency performance of a circuit (not shown) that employs the nanowire device 132.
However, minimizing the distances 162 and 164 may not be possible or may provide drawbacks. In particular, the distances 162 and 164 are provided to allow the gate material for the gate 152 to be disposed completely around and between the nanowires 142(1-N), for example. Accordingly, minimizing the distances 162 and 164 is limited by at least the process of disposing the gate material for the gate 152. Furthermore, adjacent nanowires 142(1-N) of the nanowires 142(1-N) are separated by, for example, a gate material, which generates channel parasitic capacitance. This channel parasitic capacitance increases as adjacent nanowires 142(1-N) of the nanowires 142(1-N) are set closer together, thus increasing power consumption and overall performance.
Another way to add nanowires 142(1-N) to the nanowire device 132 is by increasing a height 166 of the nanowire channel structure 140 while maintaining required minimum distances for the distances 162 and 164. This may allow more nanowires 142(1-N) in the nanowire channel structure 140. However, performance and fabrication limitations may limit the height 166 of the nanowire channel structure 140. For example, increasing the height 166 of the nanowire channel structure 140 increases parasitic parallel plate capacitance between the gate 152 and the source 136 which, as explained earlier, may increase delay of the nanowire device 132, shift the threshold voltage of the nanowire device 132, and decrease frequency performance of a circuit (not shown) employing the nanowire device 132. Furthermore, increasing the height 166 of the nanowire channel structure 140 results in a high height-to-width aspect ratio for the nanowire channel structure 140. Having a high height-to-width aspect ratio in the nanowire channel structure 140 may be undesirable for forming the nanowire channel structure 140, in particular, and the nanowire device 132, generally, and may limit scaling down the nanowire device 132. Furthermore, having additional nanowires 142(1-N) increases channel parasitic capacitance by providing additional nanowire-gate material-nanowire combinations. Therefore, performance and fabrication limitations regarding, for example, the distances 162 and 164, and the height 166, may limit further scaling down of the nanowire device 132.